1. Field of the Invention
The present invention relates to field-programmable gate arrays (FPGAs). More particularly, the present invention relates to testing for manufacturing defects in FPGA devices.
2. The Prior Art
Testing the routing tracks and switches in an FGPA device for manufacturing defects is an important part of the FPGA manufacturing process. Such defects manifest themselves in ways that may be described by fault models. Testing should be done with the best possible coverage of potential faults and the least possible test time.
Reprogrammable FPGA routing is typically tested by programming various configurations into the FPGA device and then executing test patterns for each configuration. To reduce test time, the number of configurations and the number of test patterns required for each configuration should be minimized. A test pattern is a set of specific data applied to and expected from a design which has been configured in the device.
Reprogrammable non-volatile FPGAs have generally been tested like other reprogrammable FGPAs. However non-volatile FPGAs may require more time to program each configuration than an SRAM-based FPGA. For instance, this is often true of flash-based FGPAs. It would therefore be especially advantageous for reprogrammable non-volatile FPGAs if a way can be found to achieve good coverage with fewer configurations, even if some extra circuitry or more test patterns are required.
FIG. 1 is a schematic diagram showing a typical portion of a reprogrammable routing network 10. A signal M1 on line 12 is buffered by buffer 14 to drive routing track 16 with a signal T1. In particular, FIG. 1 shows this signal drives a routing multiplexer 18 whose output is M3 on line 20. The signal T1 fans out to drive inputs of one or more routing multiplexers via lines 22 and 24. Routing multiplexer 18 receives input from other tracks, such as T2 on line 26 and selects which of signals T1 and T2 to output by turning on one of non-volatile transistor switches 28 or 30. The signal M3 on line 20 is buffered by buffer 32 to drive signal T3 on routing track 34.
The multiplexer may also be driven to a constant logic 0 (signal C0 on line 36), or to a constant logic 1 (signal C1 on line 38). The non-volatile transistor switches used for this purpose (shown at reference numerals 40 and 42) are referred to as tie-off switches. In some cases either the C0 or C1 tie-off switch may be omitted depending on the logical purpose of the particular routing multiplexer in question. In any event, one or the other is required to put the routing buffer in a fixed state when it is not needed.
Persons of ordinary skill in the art will appreciate that in FIG. 1 the switches are drawn as floating gate transistor switches 28, 30, 40 and 42, but they could also be implemented as other types of non-volatile switches, or as volatile switches such as ordinary NMOS or CMOS pass gates controlled by control bits stored in SRAM configuration memory. The use of such other non-volatile switches is specifically contemplated as being within the scope of the present invention.
For purposes of the present invention, FPGA faults may generally be classified into several categories. A list of these categories is provided in the following Table 1:
TABLE 1No.DescriptionType1Mux output (Mi) or track (Ti) stuck at 0functional2Mux output (Mi) or track (Ti) stuck at 1functional3Mux output shorted to corresponding track (Mi to Ti)functional4Routing switch stuck closedfunctional5Two or more tracks shorted (Ti to Tj, i ≠ j)functional6Two or more mux outputs shorted (Mi to Mj, i ≠ j)functional7Mux output shorted to non-correspondingfunctionaltrack (Mi to Tj, i ≠ j)8Tie-off switch stuck closedfunctional9Switch stuck openfunctional10Track open between buffer and switchfunctional11Open circuit between C0 or C1 and the tie-off switchesfunctional12High-resistance switchdelay13High-resistance trackdelay
Fault types 1 and 2 are “stuck bit” faults. Fault type 1 is where the output Mi of the routing multiplexer or the signal Ti on the input track to the routing multiplexer is stuck at a logic “0” state. Fault type 2 is where the output Mi of the routing multiplexer or the signal Ti on the input track to the routing multiplexer is stuck at a logic “1” state.
Fault type 3 is where the output Mi of the routing multiplexer is shorted to the signal Ti, the track driven by the output of the same routing multiplexer. Fault type 4 is where one of the routing non-volatile memory transistor switches (either 28 or 30 in FIG. 1) is stuck in the on position.
Fault type 5 is where two or more tracks, i.e., Ti and Tj (where i≠j) are shorted together. Fault type 6 is where the outputs of two or more multiplexers are shorted together.
Fault type 7 is where the output Mi of one routing multiplexer is shorted to a signal Tj that is normally driven by the output of another routing multiplexer. Fault type 8 is where one of the tie-off transistors (40 and 42 in FIG. 1) is stuck closed.
Fault type 9 is where one of the non-volatile memory switches is stuck open. Fault type 10 is where a track between one of the buffers and non-volatile memory switches is open. Fault type 11 is where there is an open circuit between one of the tie-off signals (C0 and C1 in FIG. 1) and an associated tie-off switch.
Fault type 12 is where the on resistance of one of the non-volatile memory transistor switches is high. Fault type 13 is where the resistance of one of the tracks is high.
Fault types 1 through 11 are referred to as functional faults because they represent physical device failures or wiring defects and the chip functions incorrectly at any speed. Fault types 12 and 13 are referred to as delay faults because the chip will still function correctly if sufficient time for signal propagation is allowed.
With a type 3 fault, the corresponding routing buffer has its input and output shorted. This would most likely manifest itself as a type 1 or 2 fault. However the type 3 fault is listed separately to make clear that all cases of shorts between multiplexer outputs and tracks have been enumerated.
Since each routing switch connects some Mi to some Tj, a type 4 fault is also a type 7 fault. However the type 4 fault is listed separately to make clear that all cases of switch faults have been enumerated.
A type 8 fault might result in a type 1 or type 2 fault if the constant input dominates any other signal connected to the multiplexer output. But this is not necessarily the case (e.g., the constant input is a logic “1” and another input can still sink the multiplexer output to ground).
A small set of a few test configurations is generally sufficient to permit each track to be controlled (i.e., driven to 0 and to 1), and each track to be observed, at least indirectly. By indirectly, it is meant that a track is considered controllable if it is driven by some other track that is controllable. A track is considered observable if it drives some other track that is observable. Such a set of test configurations covers all faults of types 1 through 3 (as well as some faults of other types).
A somewhat larger set of test configurations is generally sufficient to guarantee that for each pair of tracks Ti and Tj, i≠j, there exists a configuration in which both tracks are independently controllable and Ti is observable, and there exists a configuration (possibly but not necessarily the same configuration) in which both tracks are independently controllable and Tj is observable. This provides the ability to reliably detect shorts between the two tracks. Since Ti is driven by and Tj is driven by Mj, this also provides the ability to reliably detect shorts between Mi and Mj, between Mi and Tj, and between Mj and Ti. Thus such a set of test configurations covers all faults of types 4 through 7, as well as types 1 through 3. Most likely the set would need to contain only about a half-dozen configurations for a typical state of the art FPGA architecture. The exact number is architecture dependent.
Faults of type 8 through 11 can also be covered by a sufficiently large set of configurations. However this set would be much larger than those previously discussed, perhaps requiring two dozen or more configurations, although the exact number is architecture dependent. Also covering faults of type 12 and 13 (the delay faults) would significantly increase the number of configurations required. It would be useful if it could be made easier to cover faults of type 8 through 13.
A primary objective is to detect the existence of any fault with the fewest configurations, not necessarily to identify the location of a fault. The latter is useful, but more configurations can be used for fault location since it is not done during production testing.